1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an identification information generation circuit that generates identification information (ID) specific to a chip and an identification information generation method for a semiconductor device.
2. Description of the Background Art
As a countermeasure against imitation semiconductor devices and frauds in electronic commerce service over the Internet, specific identification information is assigned to each semiconductor chip. For example, a system is known in which, in a manufacturing process of a semiconductor chip, different data per semiconductor chip is written into a fuse or a nonvolatile memory. Another system is known in which random data held by a SRAM cell after power-on is utilized as a “fingerprint” of a semiconductor chip.
Japanese Patent Laying-Open No. 2002-278934 discloses an invention of a security protection system for a handy terminal. The handy terminal generates device identification information based on positional information on a defective block held by a built-in NAND chip.
Japanese Patent Laying-Open No. 2001-101083 discloses an invention in which a defective address of a semiconductor memory is used as a key. A server device holding contents receives a key transmitted from a client device and transmits the contents with the key inserted therein to the client device. H. Fujiwara, M. Yabuuchi, H. Nakano, H. Kawai, K. Nii, and K. Arimoto, “A Chip-ID Generating Circuit for Dependable LSI using Random Address Errors on Embedded SRAM and On-Chip Memory BIST”, 2011 Symposium on VLSI Circuits Digest of Technical Papers, Jun. 15-17, 2011, pp. 76-77 (Non-Patent Document 1) discloses a configuration in which chip ID of LSI (semiconductor integrated circuit) is generated based on a defective cell address of an embedded SRAM and an I/O bit position to which the defective cell belongs.
Y. Su, J. Holleman, B. Otis, “A 1.6 pJ/bit 96% Stable Chip-ID Generating Circuit using Process Variations”, 2007 IEEE International Solid-State Circuits Conference, pp. 406-407 and p. 611 (Non-Patent Document 2) discloses a configuration in which an original identification number (ID) is generated for each f chip using a latch circuit in which NOR logic gates are cross coupled.
In Non-Patent Document 2, an exclusive latch circuit for generating an original identification number for each chip is provided on a chip. In order to generate an identification number having a sufficient bit length, it is necessary to provide a plurality of latch circuits accordingly, thus resulting in a problem of increased chip area.